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1 ? fn7005.3 EL5825 8-channel tft-lcd reference voltage generator the EL5825 is designed to produce the reference voltages required in tft-lcd applications. each output is programmed to the required voltage with 10 bits of resolution. reference pins determine the high and low voltages of the output range, wh ich are capable of swinging to either supply rail. prog ramming of each output is performed using the serial interface. a serial out pin enables daisy chaining of multiple devices. a number of the EL5825 can be stacked for applications requiring more than 8 outputs. the reference inputs can be tied to the rails, enabling each part to output the full voltage range, or alternatively, they can be connected to external resistors to split the output range and enable finer resolutions of the outputs. the EL5825 has 8 outputs and is available in both the 24-pin tssop and the 24-pin qfn pack ages. it is specified for operation over the full -40c to +85c temperature range. features ? 8-channel reference outputs ? accuracy of 0.1% ? supply voltage of 4.5v to 16.5v ? digital supply 3.3v to 5v ? low supply current of 8ma ? rail-to-rail capability applications ? tft-lcd drive circuits ? reference voltage generators pinouts ordering information part number package tape & reel pkg. no. EL5825il 24-pin qfn - mdp0046 EL5825il-t7 24-pin qfn 7? mdp0046 EL5825il-t13 24-pin qfn 13? mdp0046 EL5825ir 24-pin tssop - mdp0044 EL5825ir-t7 24-pin tssop 7? mdp0044 EL5825ir-t13 24-pin tssop 13? mdp0044 sclk sdo osc vsd nc vs refh refl gnd nc cap nc sdi ena outa outb outc outd gnd oute outf outg outh nc EL5825 (24-pin tssop) top view 1 2 3 4 16 15 14 13 5 6 7 12 11 9 8 10 20 19 18 17 24 23 22 21 EL5825 (24-pin qfn) top view 19 18 17 16 15 14 13 24 23 22 21 20 8 9 10 11 12 1 2 3 4 5 6 7 thermal pad osc vsd nc vs refh refl gnd outb outc outd gnd oute outf outg sdo sclk sdi ena outa cap nc nc nc outh thermal pad data sheet april 19, 2004 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2004. all rights reserved. elantec is a registered trademark of elantec semiconductor, inc. all other trademarks mentioned are the property of their respective owners.
2 important note: all parameters having min/max specifications are guaranteed. typ values are for information purposes only. unles s otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a absolute maxi mum ratings (t a = 25c) supply voltage between v s and gnd. . . . . . . . . . . . . . . . . . . .+18v supply voltage between v sd and gnd . . . . . . . v s and +7v (max) maximum continuous output current . . . . . . . . . . . . . . . . . . . 30ma ambient operating temperature . . . . . . . . . . . . . . . .-40c to +85c power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see curves maximum die temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. electrical specifications v s = 15v, v sd = 5v, v refh = 13v, v refl = 2v, r l = 1.5k ? and c l = 200pf to 0v, t a = 25c, unless otherwise specified. parameter description conditions min typ max unit supply i s supply current no load 7.6 9 ma i sd digital supply current 0.17 0.35 ma analog v ol output swing low sinking 5ma (v refh = 15v, v refl = 0) 50 150 mv v oh output swing high sourcing 5ma (v refh = 15v, v refl = 0) 14.85 14.95 v i sc short circuit current r l = 10 ? 100 140 ma psrr power supply rejection ratio v s + is moved from 14v to 16v 45 60 db t d program to out delay 4ms v ac accuracy 20 mv v droop droop voltage 12mv/ms r inh input resistance @ v refh , v refl 34 k ? reg load regulation i out = 5ma step 0.5 1.5 mv/ma bg band gap 1.1 1.3 1.6 v digital v ih logic 1 input voltage v sd - 20% v v il logic 0 input voltage 20%* v sd v f clk clock frequency 5mhz t s setup time 20 ns t h hold time 20 ns t lc load to clock time 20 ns t ce clock to load line 20 ns t dco clock to out delay time negative edge of sclk 10 ns r sdin s din input resistance 1g ? EL5825
3 pin descriptions 24-pin qfn 24-pin tssop pin name pin type pin description 1 3 osc ip/op oscillator pin for synchronizing multiple chips 2 4 vsd power positive power supply fo r digital circuits (3.3v - 5v) 3 5 nc not connected 4 6 vs power positive supply vo ltage for analog circuits 5 7 refh analog input high reference voltage 6 8 refl analog input low reference voltage 7 9 gnd power ground 8 11 cap analog decoupling capacitor for internal reference generator, 0.1f 9 10 nc not connected 10 12 nc not connected 11 13 nc not connected 12 14 outh analog output channel h programmable output voltage 13 15 outg analog output channel g programmable output voltage 14 16 outf analog output channel f programmable output voltage 15 17 oute analog output channel e programmable output voltage 16 18 gnd power ground 17 19 outd analog output channel d programmable output voltage 18 20 outc analog output channel c programmable output voltage 19 21 outb analog output channel b programmable output voltage 20 22 outa analog output channel a programmable output voltage 21 23 ena logic input chip select, low enables data input to logic 22 24 sdi logic input serial data input 23 1 sclk logic input serial data clock 24 2 sdo logic output serial data output EL5825
4 typical performance curves figure 1. differential nonlinearity vs code figure 2. digital supply current vs digital supply voltage figure 3. supply current vs supply voltage figure 4. transient load regulation (sourcing) figure 5. transient load regulation (sinking) figure 6. large signal response (rising from 0v to 8v) 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 10 210 410 610 810 1010 input code differential nonlinearity (lsb) v s =15v v sd =5v v refh =13v v refl =2v 180 140 100 60 40 20 0 33.544.555.5 v sd (v) i sd (na) 160 120 80 7.2 7 6.6 6.2 6 5.8 5.6 4 6 8 12 14 16 18 v s (v) i s (ma) v out =0v 6.8 6.4 10 0ma 5v 5ma/div 200mv/div 5ma c l =180pf c l =4.7nf r s =20 ? c l =1nf r s =20 ? v s =v refh =15v m=400ns/div 5ma 0ma c l =1nf r s =20 ? c l =180pf v s =v refh =15v m=400ns/div c l =4.7nf r s =20 ? sclk sda ena outa m=200s/div EL5825
5 figure 7. small signal response (falling from 200mv to 100mv) figure 8. package power dissipation vs ambient temperature figure 9. package power dissipation vs ambient temperature figure 10. package power dissipation vs ambient temperature figure 11. package power dissipation vs ambient temperature typical performance curves (continued) sclk sda ena outa m=200s/div 1.4 0 ambient temperature (c) power dissipation (w) 1.2 1 0.8 0.6 0.4 0.2 0 25 50 75 100 125 85 1.176w j a = 8 5 c / w t s s o p 2 4 jedec jesd51-7 high effective thermal conductivity test board 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 255075100125 ambient temperature (c) power dissipation (w) 85 781mw j a = 1 2 8 c/ w t s s o p 2 4 jedec jesd51-3 low effective thermal conductivity test board jedec jesd51-7 high effective thermal conductivity test board - qfn exposed diepad soldered to pcb per jesd51-5 3 2.5 2 1.5 1 0.5 0 0 255075100 150 ambient temperature (c) power dissipation (w) 2.703w j a = 3 7 c / w q f n 2 4 125 85 jedec jesd51-3 and semi g42-88 (single layer) test board 0.8 0.7 0.5 0.3 0.2 0.1 0 0 255075100 150 ambient temperature (c) power dissipation (w) 714mw j a = 1 4 0 c / w q f n 2 4 125 85 0.6 0.4 EL5825
6 product description the EL5825 provides a versatile method of providing the reference voltages that are used in setting the transfer characteristics of lcd display panels. the v/t (voltage/transmission) curve of the lcd panel requires that a correction is applied to make it linear; however, if the panel is to be used in more than one application, the final curve may differ for different applications. by using the EL5825, this cu rve can be changed to optimize its characteristics according to the required application of the display product. each of the reference voltage outputs can be set with a 10-bit resolution. these outputs are available to within 100mv of the power rails of the EL5825. as all of the output buffers are identical, it is also possible to use the EL5825 for applications other than lcds where 8 voltage references are required that can be set to a 10-bit accuracy. serial interface the EL5825 is programmed through a three-wire serial interface. the start and stop conditions are defined by the ena signal. while the ena is low, the data on the sdi (serial data input) pin is shifted into the 16-bit shift register on the positive edge of the sclk (serial clock) signal. the msb (bit 15) is loaded first and the lsb (bit 0) is loaded last (see table 1). after the full 16-bit data has been loaded, the ena is pulled high and the addressed output channel is updated. the sclk is disabled internally when the ena is high. the sclk must be low before the ena is pulled low. to facilitate the system designs that use multiple EL5825 chips, a buffered serial output of the shift register (sdo pin) is available. data appears on the sdo pin at the 16th falling sclk edge after being applied to the sdi pin. to control the multiple EL5825 chips from a single three-wire serial port, just connect the ena pins and the sclk pins together, connect the sdo pin to the sdi pin on the next chip. while the ena is held low, the 16m-bit data is loaded to the sdi input of the first chip. the first 16-bit data will go to the last chip and the last 16-bit data will go to the first chip. while the ena is held high, all addressed outputs will be updated simultaneously. the serial timing diagram and parameters table show the timing requirements for three-wire signals. the serial data has a minimum length of 16 bits, the msb (most significant bit) is the firs t bit in the signal. the bits are allocated to the following functions (also refer to the control bits logic table) ? bit 15 is always set to a zero ? bit 14 controls the source of the clock, see the next section for details ? bits 13 through 10 select the channel to be written to, these are binary coded with channel a = 0, and channel h= 7 ? the 10-bit data is on bits 9 through 0. some examples of data words are shown in the table of serial programming examples table 1. control bits logic table bit name description b15 test always 0 b14 oscillator 0 = internal, 1 = external b13 a3 channel address (don?t care) b12 a2 channel address b11 a1 channel address b10 a0 channel address b9 d9 data b8 d8 data b7 d7 data b6 d6 data b5 d5 data b4 d4 data b3 d3 data b2 d2 data b1 d1 data b0 d0 data EL5825
7 serial timing diagram internal refresh clock oscillator the EL5825 requires an internal clock or external clock to refresh its outputs. the outputs are refreshed at the falling osc clock edges. the output refreshed switches open at the rising edges of the osc clock. the driving load shouldn?t be changed at the rising edges of the osc clock. otherwise, it will generate a voltage error at the outputs. this clock may be input or output via the clock pin labeled osc. the internal clock is provided by an internal oscillator running at approximately 25khz and can be output to the osc pin. in a multiple chip system, if the driv ing loads are stable, one chip may be programmed to use the internal oscillator; then the osc pin will output the clock from the internal oscillator. subsequent chips may have the osc pin connected to this clock source. in these chips, the program will set them to external osc mode by setting bit 14 to 1. see the control bits logic table and serial programming example for details. for transient load application, the external clock mode should be used to ensure all functions are synchronized together. the positive edge of the external clock to the osc pin should be timed to avoid the transient load effect. the application drawing on page 10 shows the lcd h rate signal used, here the positive clock edge is timed to avoid the transient load of the column driver circuits. after power on, the chip will start with the internal oscillator mode. at this time, the osc pin will be in a high impedance condition to prevent contention. after programming the table 2. serial timing parameters parameter example description t 200ns clock period t r /t f 0.05 * t clock rise/fall time t he 10ns ena hold time t se 10ns ena setup time t hd 10ns data hold time t sd 10ns data setup time t w 0.50 * t clock pulse width b15 b14 b13 b12-b2 b1 b0 ena sclk sdi msb lsb t t he t se t sd t hd tt r t w t he t se load msb first, lsb last t f table 3. serial programming examples control channel address data condition c1 c0 a3 a2 a1 a0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 x0000000000000internal oscillator, ch annel a, value = 0 0 0 x0001111111111internal oscillator, c hannel a, value = 1023 0 0 x0001000000000internal oscillator, ch annel a, value = 512 0 0 x0111000000001internal oscillator, ch annel c, value = 513 0 0 x1110000011111internal oscillator, ch annel h, value = 31 0 1 x1110000011111external oscillator, c hannel h, value = 31 EL5825
8 oscillator with bit 14, the pin will be set to the appropriate mode. transfer function the transfer function is: where data is the decimal value of the 10-bit data binary input code. the output voltages from the EL5825 will be derived from the reference voltages present at the v refl and v refh pins. the impedance between t hose two pins is about 32k ? . care should be taken that the system design holds these two reference voltages within the limits of the power rails of the EL5825. gnd < v refh v s and gnd v refl v refh . in some lcd applications that require more than 8 channels, the system can be designed such that one EL5825 will provide the gamma correction voltages that are more positive than the v com potential. the second EL5825 can provide the gamma correction voltage more negative than the v com potential. the application drawing on page 10 shows a system connected in this way. block diagram channel outputs each of the channel outputs has a rail-to-rail buffer. this enables all channels to have the capability to drive to within 100mv of the power rails, (see electrical characteristics for details). when driving large capacitive loads, a series resistor should be placed in series with the output. (usually between 5 ? and 50 ? ). each of the channels is updated on a continuous cycle, the time for the new data to appear at a specific output will depend on the exact timing relationship of the incoming data to this cycle. the best-case scenario is when the data has just been captured and then passed on to the output stage immediately; this can be as short as 40s. in the worst-case scenario this will be 320s, when the data has just missed the cycle. v out ideal ) ( v refl = data 1024 ------------ - v refh - v refl () + voltage sources eight channel registers control if serial data input serial clock enable oscillator input/output3 serial data output cap reference low outh outg outf oute outd outc outb outa reference high EL5825
9 when a large change in output voltage is required, the change will occur in 2 volt steps, thus the requisite number of timing cycles will be added to the overall updat e time. this means that a large change of 16 volts can take between 2.56 milliseconds and 3 milliseconds depending on the absolute timing relative to the update cycle. power dissipation with the 30ma maximum continues output drive capability for each channel, it is possible to exceed the 125c absolute maximum junction temperature. therefore, it is important to calculate the maximum junction temperature for the application to determine if load conditions need to be modified for the part to remain in the safe operation. the maximum power dissipation allowed in a package is determined according to: where: ?t jmax = maximum junction temperature ?t amax = maximum ambi ent temperature ? ja = thermal resistance of the package ?p dmax = maximum power dissipation in the package the maximum power dissipation actually produced by the ic is the total quiescent supply current times the total power supply voltage and plus the power in the ic due to the loads. when sourcing, and: when sinking. where: ? i = 1 to total 8 ?v s = supply voltage ?i s = quiescent current ?v out i = output voltage of the i channel ?i load i = load current of the i channel by setting the two p dmax equations equal to each other, we can solve for the r load 's to avoid the device overheat. the package power dissipation curves provide a convenient way to see if the device will overheat. power supply bypassing and printed circuit board layout good printed circuit board layo ut is necessary for optimum performance. a low impedance and clean analog ground plane should be used for the EL5825. the traces from the two ground pins to the ground plane must be very short. the thermal pad of the EL5825 should be connected to the analog ground plane. lead length should be as short as possible and all power supply pins must be well bypassed. a 0.1f ceramic capacitor must be place very close to the v s , v refh , v refl , and cap pins. a 4.7f local bypass tantalum capacitor should be placed to the v s , v refh , and v refl pins. application using the EL5825 in the application drawing, the schematic shows the interconnect of a pair of EL5825 chips connected to give 8 gamma corrected voltages above the v com voltage, and 8 gamma corrected voltages below the v com voltage. by using the serial data out pin, it is possible to daisy chain (cascade) the two chips. in th is mode the micro-controller will send a 32-bit word that will update both the upper and lower references voltages in one operation. see application drawing 1 for details. p dmax t jmax - t amax ja -------------------------------------------- - = p dmax v s i s v s ( - v out i ) i load i [] + = p dmax v s i s v out ii load i () + = EL5825
10 application drawing serial timing diagram (32 bit) refh vs vsd sdi sclk ena sdo osc cap refl outa outb outc outd oute outf out outh refh osc vs vsd sdi sclk ena cap refl outa outb outc outd oute outf out outh micro- controller column (source) driver 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f middle reference voltage high reference voltage serial data serial data clock enable serial data serial data serial data clock enable low reference voltage +1v +10v +5.5v +12v +5v +12v +5v EL5825 lcd panel gnd gnd lcd timing controller horizontal rate EL5825
11 qfn package outline drawing EL5825
12 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com tssop package outline drawing note: the package drawing shown here may not be the latest version. to check the latest revision, please refer to the intersil w ebsite at EL5825

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